Novel approach to design low power low noise CMOS Amplifier

In recent years, there have been growing demands for bandwidth, for both voice and data communications. This has increased the need for high speed systems. The Radio Frequency integrated circuit (RFIC) and wireless market has suddenly expanded to unimaginable dimensions. Devices such as pagers, cellular and cordless phones, cable modems, and RF identification tags are rapidly penetrating all aspects of our lives, evolving from luxury items to indispensable tools. Historically, RFIC’s are implemented in III-V compounded semiconductors or in bipolar technologies. The DSP circuits, on the other hand, require small feature sizes to guarantee high speed of operation with low power consumption, hence the use of Complementary Metal-Oxide Semiconductor (CMOS) technologies. CMOS technologies are beginning to satisfy the needs of high-speed analog design, providing the drive for the quest for a complete commercial CMOS transceiver. Driven by the needs for low power, small size and low cost, CMOS RFIC design becomes main stream in modern wireless communication.The challenges are not only to design RF transceivers in CMOS processes, but also to establish design methodologies.